The use of configurable integrated circuits (“ICs”) has dramatically increased in recent years. Configurable ICs can be used to implement circuits designed by a user (“user design”) on an IC without having to fabricate a new IC for each design. One example of a configurable IC is a field programmable gate array (“FPGA”). A configurable IC has several circuits for performing different operations. Configurable circuits can be configured by configuration data to perform a variety of different operations. These circuits can range from logic circuits (e.g., configurable lookup tables, or “LUTs”) to interconnect circuits (e.g., configurable multiplexers). The circuits of a configurable IC are often made up of a multitude of transistors.
The circuits of a configurable IC are typically fabricated on a semiconductor substrate. Almost any integrated circuit design requires connections from transistors on one part of the substrate to transistors on other parts of the substrate. These transistors are often connected by small metal or polysilicon wires that traverse several wiring layers above a substrate. Such connections can also include vias that allow signals from one wiring plane to pass to another wiring plane.
Connections between circuits in a configurable IC often have inline buffers that serve several purposes. For example, a buffer may be used to regenerate signals passing along a set of wires, or to increase the current drive for driving a signal by a certain factor. This factor is referred to as “fan out” (e.g., a fan out of 3 means a buffer provides 3 times the current drive at its output as it receives at its input). It has been found that an optimal fan out is Euler's number (e), or approximately 2.7. As an approximation of e, a fan out of three is commonly used. For example, if a total fan out of 27 is desired, a first buffer is used to provide a current drive at its output that is 3 times the current drive at the buffer's input. A second buffer increases the current drive by 3 times (resulting in a 9 times increase from the original current drive), and a third buffer increases the current drive by 3 times (resulting in the desired 27 times increase).
Buffers consume dynamic power in order to operate. Buffers are powered by a power source that supplies a certain voltage (VPS). Dynamic power is consumed when a buffer's transistor's output switches from low to high, or vice versa. This voltage difference is referred to as swing voltage (Vswing). The amount of dynamic power consumed by a buffer is directly proportional to C*VPS*Vswing*f, where C is the capacitance being driven by the buffer, VPS is the voltage supplied to the buffer, and f is the frequency.
As circuits progressively become smaller and more densely packed on an IC, power consumption becomes an issue, as the existence of more circuits inevitably leads to greater power requirements. Furthermore, power consumption increases as operational speed increases. One currently existing method of saving power in an IC is to simply lower the operational voltage VPS of the IC. However, reducing VPS yields the undesirable effect of reducing current in the IC and introducing delay, thus resulting in an overall performance loss. Another method for reducing the amount of dynamic power consumed includes variably reducing VPS in accordance with the power needs of the IC. However, this approach is often based on heuristics which may not be accurate for determining (1) when to reduce or increase supplied power, and (2) how much power should be increased or decreased. Another approach for reducing power uses voltage islands. However, this approach requires a great deal of overhead, thus reducing performance. Using voltage islands also limits flexibility in designing ICs, as the IC must be built and configured in order to accommodate the voltage islands.
Additionally, leakage current is becoming more problematic as smaller devices (e.g., smaller transistors) and thinner dielectric materials (e.g., thinner oxides) are being used. Leakage is the flow of current through a transistor even when the transistor is “off” For example, when a PMOS transistor is in its off state, the difference between its gate and source voltages (VGS) is zero. However, notwithstanding this zero gate-source voltage VGS, the PMOS transistor still experiences a small amount of current flow (i.e., leakage). This leakage problem is exacerbated when (1) its threshold voltage VT is lowered, and/or (2) a thinner dielectric material (e.g., a thinner oxide) is used for the transistor. While a lower threshold voltage provides a faster switching PMOS transistor, the lower threshold voltage also causes an increase in the amount of leakage current that the PMOS transistor experiences in its off state. Similarly, transistors with thinner oxides—while faster-switching than transistors with thicker oxides—are leakier than their thicker-oxide counterparts (i.e., they experience more current leakage in their off state).
Therefore, there is a need in the art for a way to save power in an IC without reducing performance or introducing leakage current.